以上来源于: WordNet
Sequential logic synthesis is an important part of RTL synthesis system design.
时序逻辑综合是RTL综合系统设计中的一个重要部分。
The second is where you have to integrate the loop closely with the sequential logic.
第二点是,人们必须将一些控制环与顺序逻辑控制更紧密地集成。
This experimental quide to the digital logic comprises two parts: combinational logic and sequential logic.
本实验指导书分为两大部分:组合逻辑,时序逻辑。
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