semiconductor dual in-line package 半导体双直插组件
Bottom lead semiconductor chip package 发明名称
semiconductor dual inline package 半导体双列插式组件
以上来源于: WordNet
A joining method, a method of mounting a semiconductor package (PKG) using the same, and a substrate-joining structure prepared thereby are provided.
本发明提供了一种接合方法、采用该方法安装半导体封装(pkg)的方法以及由此制备的基底接合结构。
A semiconductor package substrate for preventing deformation mainly comprises a flexible dielectric layer, a plurality of pins, at least one reinforced metal pattern and a solder mask layer.
一种改善变形的半导体封装基板,主要包括一可挠性介电层、多数个引脚、至少一补强金属图案以及一防焊层。
This review introduces the program package LADIA for lattice distortion analysis and its application to semiconductor self-assembled quantum dot (QD) systems.
本综述介绍晶格畸变分析(LADIA)程序包及其在半导体自组装量子点(QD)系统中的应用。
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