A PLL based on self-biased technology is designed and fabricated in 90 nm CMOS process. The PLL could output low jitter clock signal in a wide input frequency range.
用90nmCMOS工艺设计实现了一个基于自偏置技术的时钟锁相环,锁相环可以在很宽的输入频率范围内输出低抖动的时钟信号。
参考来源 - 低抖动时钟锁相环的一种优化设计方法·2,447,543篇论文数据，部分数据来源于NoteExpress
The design method of self-biased circulator with coplanar waveguide structure was also studied.
最后，研究了共面波导自偏置环行器的设计方法。
In this paper, a low-jitter process-independent DLL(delay locked loop) based on self-biased techniques is presented.
本文给出了一种采用自偏置技术的低抖动延迟锁相环，可应用于高频时钟产生电路。
The experiment was not very rigorous: the demographic of the room was certainly biased towards the more senior generations, and the respondents from this group were all self-selecting.
这实验并非十分严格：房间里的人们肯定偏向年长的一代，并且团队里的受访者均为自愿。
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