...块、串/并转换模块(S/P)、并/串转换模块(P/S)、先入先出存储器模块（fifo_in、fifo_out）、Sdram存储器控制接口（Sdram control）、DMA控制器接口（Dma_in、Dma_out）和用于接收按键信息的通用并行接口（pio）模块等。
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Structure and work principle of SDRAM chip (MT48LC16M16A2TG-75IT) is analyzed. Internal architecture and workflow of SDRAM controller is confirmed. Furthermore, its control and data path is designed.
分析了SDRAM芯片(MT 48lc16 M 16a2tg - 75it)的结构和工作原理，确定了内存sdram控制器的内部结构和工作流程，完成了内存sdram控制器的控制通路和数据通路设计。
This article introduces that in a new design of radar raster-displaying terminal, SDRAM is used as video frame memory and FPGA is adopted to carry out the process of control circuit.
SDRAM作为雷达光栅显示视频帧缓冲存储器，通过FPGA器件实现对SDRAM的控制，已成功应用于一款雷达光栅显示终端。
The SDRAM has become the chief choice of the buffer storage because of its high speed, great capacity, and low price; but due to its complex control timing, it cannot directly interface with DSP.
同步动态随机存储器（SDRAM）具有高速，大容量，价格低廉等优点，因而成为缓冲存储器的首选，但是SDRAM控制时序比较复杂，不能与DSP直接接口，这极大地限制了它的广泛应用。
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