SCFL circuits are used because of the higher speed compared to static CMOS.

电路采用源极耦合场效应管逻辑（SCFL），与静态CMOS逻辑相比具有更高的速度。

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In order to meet with the requirements of high-speed, the source coupled FET logic (SCFL) is applied in all of the circuits.

为了适应高速度的要求，所有电路全都采用源极耦合场效应管逻辑来实现。

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The decision circuit of the chip is applied with a DFF using SCFL structure and its tuned phase shifter with differential current amplifiers according to the principle of vector addition.

该芯片的判决电路采用SCFL(源级耦合晶体管逻辑)的D触发器结构，根据矢量叠加原理设计，采用差动电流放大器构成可调移相器。

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