On the basis of research on the bound ary-scan architecture and TAP controller, the paper implements a design for a t ap interface based on JTAG specification in a test system.
该文在研究边界扫描体系结构和TAP接口控制器的基础上，在一个测试系统中，实现了基于JTAG规范的主ta P接口设计。
In this paper, the theory and architecture of boundary scan test technology is introduced and researched, then its application is given.
研究了目前较常用的边界扫描测试技术的原理、结构，并给出了边界扫描技术的应用。
In CAVLC architecture, we improve the longer scan period of the previous architecture. Also we utilize simple logic operations to compute the address of coding and reduce the coding period .
而在基于上下文之可变长度编码架构上，我们改善了先前架构过长的扫描周期，采用简单的逻辑运算，运算出需编码的位置，使得编码周期大大的缩短。
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