It’s composed of a sample-and-hold circuit, eight stages with 1.5bit per stage, and a 2 bit flash ADC as last stage.
该模数转换器采用采样保持电路、八级1.5位和最后一级2位子模数转换器的结构,电路使用全差分和开关电容电路技术。
参考来源 - 一种高速流水线结构模数转换器的设计·2,447,543篇论文数据,部分数据来源于NoteExpress
以上来源于: WordNet
The output of the sample-and-hold system now goes into an analog-to-digital converter .
取样和保持系统的输出现在又进入一个模数转换器。
A low supply voltage sample-and-hold circuit for a pipelined analog-to-digital converter is described.
设计了一个用于流水线型模数转换器的低压采样保持电路。
Sampling rate and holding accuracy are two most concerned targets in designing the sample-and-hold circuit.
采样速度和保持精度,是采样保持电路设计制作者最为关注的两项指标。
应用推荐