The implementation carries out the standard-cell design of RS decoder, improves the velocity of decoding efficiently and simplifies the hard - ware design.
该方法实现译码器的标准单元化设计，并且有效提高译码的速度，简化硬件设计。
In more research, a new multiplex pipeline is presented and is used to design multi-channel RS decoder. The proposed scheme greatly reduce resources per channel.
在达到设计要求的基础上本文对RS译码器做了进一步的研究，利用一种新型的复用流水线结构实现了多路RS译码器，有效的减少了每路译码所占用的资源。
By selecting the bit parallel multiplier based on WDB and the modified BM iterative algorithm that can avoid inversion, the widely used rs decoder is constructed.
采用了一种可以避免求逆运算的修正BM迭代算法，并且利用这样的迭代算法和基于弱对偶基的比特并行乘法器构成了广泛应用的RS码的译码器。
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