Fence command associated data may be stored in a fence register of the addressed register pair.
围篱指令相关数据可被储存在寻址寄存器对的围篱寄存器。
A GPU pipeline is synchronized by sending a fence command from a first module to an addressed synchronization register pair.
一种图形处理单元流水线，通过传送来自第一模块的围篱指令至寻址同步寄存器对而执行同步。
The effective address is, under the hood, always split into a pair of 32-bit registers; the high-order register is optional and if it's not specified, it is treated as zero.
在这种情况下，有效地址总是分为两个32位的寄存器；高位寄存器是可选的，如果没有指定，就会被当作零进行处理。
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