The programmable logical device has big scale, quick working speed and is programmable which is extremely suitably used to realize DDS.
可编程逻辑器件具有器件规模大、工作速度快及可编程的硬件特点，非常适合用来实现DDS。
This paper mainly talks about designing the protocol layer of USB2.0 with the programmable logical device as the carrier through the VHDL language.
本文在此主要通过VHDL语言，利用可编程逻辑器件作为载体来设计usb2.0的协议处理层模块。
Based on a complicated programmable logical device (CPLD), a miniaturized universal pulse height analysis (PHA) module of high performance is realized.
介绍一种基于复杂可编程逻辑器件(CPLD)的通用高性能脉冲幅度分析(PHA)模块设计。
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