The pipelining technique described above is an example of using asynchronous processing to enhance performance.

本文介绍的流水线技术是使用异步处理以提高性能的示例。

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This paper presents an efficient design of AES algorithm's IP core in FPGA using pipelining technique and optimized methods.

文章基于FPGA采用流水线技术和优化设计，提出了一种更高效的AES算法IP核的设计方法。

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The technique exploits pipelining from complex loop structures, which distinguishes itself from traditional pipelining techniques.

该技术与传统流水技术的不同在于，能从复杂的循环结构中发掘流水并行。

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