专业释义英英释义
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数字锁相环 - 引用次数：80
Thirdly, a digital phase-locked loop (DPLL) method is developed.
第三,深入探讨了一种数字锁相环的实现方法。
参考来源 - 户用式光伏并网发电控制策略的研究锁相回路 - 引用次数：1 参考来源 - 基于cPCI的实时相角测量装置的实用化开发锁相环 -
锁相环锁相迴路
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锁相环
·2,447,543篇论文数据，部分数据来源于NoteExpress
Phase-locked loop
- abstract: A phase-locked loop or phase lock loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input signal. While there are several differing types, it is easy to initially visualize as an electronic circuit consisting of a variable frequency oscillator and a phase detector.
以上来源于: WordNet
双语例句
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Phase-locked loop (PLL) has been applied in many fields.
锁相环在很多领域都得到了广泛应用。
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A fast all digital phase-locked loop with automatic modulus control is presented.
提出了一种具有自动变模控制的快速全数字锁相环。
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In this thesis the basic architecture and the performance evaluation of phase-locked loop are presented.
本文研究了锁相环的基本结构与系统构架及其性能优劣。
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