A design-for-testability scheme is presented for conditional sum adders with low hardware cost and low size of test set which can guarantee single-path sensitizable testability by exploiting their structural property and parallel testing.
对条件和加法器电路结构的可测性分析表明,原有结构无法实现通路的完全可测和难以实现高效的并行测试。
参考来源 - 算术运算电路的通路时延故障测试·2,447,543篇论文数据，部分数据来源于NoteExpress
Parallel testing is a crucial language element in TTCN-3.
并行测试是TTCN - 3语言中重要的语言特性。
Production data is also an excellent source for parallel testing.
生产数据也是并行测试的一个极好来源。
The existing issues in traditional parallel testing methods for PCBs interconnect faults are pointed out.
文章分析了现有的电气网络互连故障的并行测试方法，指出它们在故障诊断上的局限性。
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