This paper designs and implements an engine system of packet classification applying the parallel classifying algorithm, in which network processor is the hardware core.

本文以网络处理器为硬件核心，结合提出的并行包分类算法，设计和实现了一个包分类引擎系统。

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This paper proposed a packet processing engine architecture called NRS05, that promotes the efficient dynamic thread scheduling for hiding long latency operations and coping with pipeline stalls.

本文介绍了一个专门面向网络协议处理的硬件多线程包处理微引擎NRS05的设计。

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Applying A2BV algorithm, a high speed packet classification engine is presented based on IXP2400.

以IXP2400为硬件核心，运用A2BV算法设计和实现了一个高速包分类引擎系统。

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