This paper presents design and implementation of the simulation module in a logic-level VHDL simulation system.

介绍了VHDL逻辑级模拟系统中模拟模块的设计和实现。

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The LOP circuit module is described in gate level with VHDL, which has passed the logic simulation and verification. It is applied to the design of floating-point adder.

LOP电路设计采用VHDL语言门级描述，已通过逻辑仿真验证，并在浮点加法器的设计中得到应用。

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The three key modules are all presented as RTL level design and module functional simulation. The deinterlacing system's FPGA design is in the last chapter.

本文对于这三个去隔行系统的关键模块都给出了RTL级设计和模块的功能仿真，并在最后一章中给出了去隔行系统的FPGA设计。

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