Logical F low 逻辑布局
It is desirable to keep the logical model as free as possible from low-level detail — essentially "implementation free."
将逻辑模型尽可能地摆脱低层细节——本质上是“摆脱实现”——是令人想要的。
According to the technology of direct digital synthesis(DDS), a kind of low frequence signal source was introduced based on the Complex Programmed Logical Device(CPLD)and Single Chip Micyoco(SCM).
介绍了一种应用直接数字频率综合器(DDS)技术,基于可编程逻辑器件(CPLD)和单片机设计的低频信号源。
This protocol provides low delay and low overhead by using segmentation and reassembly and by combining information from different logical channels in a single packet.
本协议通过使用分割与重新装配并通过在单一信息包中组合来自不同逻辑信道的信息来提供低延迟和低开销。
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