abstract:The method of logical effort, a term coined by Ivan Sutherland and Bob Sproull in 1991, is a straightforward technique used to estimate delay in a CMOS circuit. Used properly, it can aid in selection of gates for a given function (including the number of stages necessary) and sizing gates to achieve the minimum delay possible for a circuit.
"For junior technology roles, often the emphasis is on logical skills, which may put girls off, but most systems these days are put together as part of team effort, " she said.