logic design translator 逻辑设计译码器
logic level translator 逻辑电平转换器
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This paper describes the partitioning of the set pf the Boolean equations generated by the hardware logic translator and the conversion of the subset into cube arrays.
本文阐明将硬件逻辑翻译器产生的布尔方程集合划分成子集后，转换成多维体列阵。
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