...—多数参数都要分别讨论高低电平下的情况 a、正逻辑（positive logic）和负逻辑（negative logice） b、逻辑电平（logic levels）的定义； c、噪声容限（noise margins）； d、阻性负载（resistive loads）下的讨论：扇入（fan-in）、扇出（fan-out）以及灌电 ...
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Logic Levels and Noise Margins 逻辑电平和噪声容限
Care must be taken when connecting logic circuits to ensure that their logic levels and current ratings are compatible.
连接逻辑电路时，必须小心翼翼，以保证他们的逻辑电平和电流额定值是兼容的。
In this notation we have explicitly taken account of the fact that in normal operation, as we shall see, the logic levels at the output are complementary.
通过这种表示方式，我们已经明显考虑这样的事实：在通常的运算中，输出的逻辑电平是互补的。
Some new low-noise edge triggered flip-flops are presented, and their logic levels are realized in the current domain by steering a constant dc bias current.
提出以电流信号表示逻辑值的新型低噪声触发器设计，用于高性能混合集成电路的设计中以减少存贮单元开关噪声对模拟电路性能的影响。
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