A variable step uniform quantization(VSUQ) sum-product algorithm(SPA) was developed to reduce the hardware complexity of low-density parity-check(LDPC) code decoding.
为降低低密度奇偶检验码译码的硬件实现复杂度，提出了一种可变步长均匀量化“和积”译码算法。
To improve the decoding performance of Low Density Parity Check (LDPC) code, an efficient decoding algorithm based on min-sum algorithm is proposed.
针对低密度奇偶校验(LDPC)译码算法性能低的问题，提出一种基于最小和的高效译码算法。
An encoder architecture of low density parity check (LDPC) code defined in DVB-S2 standard is proposed.
针对DVB - S2标准中的低密度奇偶校验(LDPC)码，提出了一种LDPC编码器设计结构。
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