The issue of interconnect capacitance rising from very large scale integration(VLSI)with a decreased feature size and increased number of wiring layers is described.

阐述了超大规模集成电路（ VLSI）特征尺寸的减小及互连线层数增加引起的互连线电容增加的问题。

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The optimal settings can be incorporated into our driving scheme so that low voltage and current requirements can be met for very large scale integration(VLSI)implementation.

优化设置可以溶入我们的驱动方案中，使得低电压和低电流可以满足大规模集成（VLSI）的要求。

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Very large-scale integration (VLSI) vastly increased circuit density, giving RisE to the microprocessor.

大规模集成电路更大的增加了微处理器的电路密度。

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