ks-l3 绿色3号
L3 bus L3总线
L3 gene L3基因
L3 events L3事例
L3 System L3级系统
L3 switch L3交换
L3 handoff L3切换
MPLS L3 VPN 第三层虚拟专用网
On-chip L3 directory and memory controller.
芯片上L 3目录和内存控制器。
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L3 directory on chip reduces off-chip delays after an L2 miss.
芯片上L 3目录可以减少发生l2未命中之后的离片延迟。
This can also improve performance by reducing L3 cache and memory contention.
这样做还可以通过减少L3缓存和内存争用，从而改善了性能。
The Celerons all have 2MB of L3 cache, HD graphics and range from 2.3GHz to 2.7GHz.
ENGADGET: Intel Ivy Bridge now available in budget-friendly silicon
Regardless of its size, the L3 II at least feels as if it's made with solid build quality.
ENGADGET
Last but certainly not least, the 3.2GHz Core i3 tops the lot with 3MB of L3 cache and HD 2500 graphics.
L3-interface是一种串行接口，最常见的实例是UDA1341TS中连接microcontroller和UDA1341TS的接口。 当然，L3有3根引脚： · L3DATA: microcontroller interface data line · L3MODE: microcontroller interface mode line · L3CLOCK: microcontroller interface clock line. 拥有地址模式和数据传输模式。
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