This paper presents a new method of asynchronous design is illustrated by the symbolic Karnaugh map.

本文提出一种异步时序电路设计的符号卡诺图的新方法。

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Besides, the Karnaugh map method and algebra method are presented for designing component level circuits.

此外，本文提出元件级电路设计的卡诺图方法和代数方法。

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This paper discusses the foundation and the application of reduced-dimension Karnaugh map in numeral logical circuit design.

文章介绍了在数字逻辑电路设计中降维卡诺图的建立和应用。

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