Moreover, a scan test circuit was proposed. This circuit can implement scan test and high speed build in self test (BIST) for IP core chip tests.

另外，本文还针对IP核投片测试提出一种扫描测试电路结构，能够实现测试芯片的扫描测试和高速内建自测试(BIST)。

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Experiments show that this testing frame can make an effective test on IP cores and take SOC environment of IP core into account while keeping high code coverage.

通过实验验证，该测试方法能够在保证一定代码覆盖率的前提下，对IP核进行有效的测试，并提高了测试后IP核的可移植性。

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And finally, simulation results and verification by hardware test in FPGA show that the design of the IP core is valid and the proposed optimization strategy to reduce the memory is effective.

对以上优化设计方案进行了设计实现。仿真结果及FPGA硬件测试验证表明，文章提出的优化方案可行、有效，极大地降低了硬件资源占用和功耗。

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