此两种简单的管线及上纯量设计，均能透过允许单一处理器在一个时脉循环完成一个指令（Instruction per cycle, IPC）[ipcrate] ，提升指令管线化的效能。
基于8个网页-相关网页
对于以平均每周期执行指令数（Instruction per cycle, IPC）值较佳的Athlon64X2处理器，再加上双核心的协助，却因为频率仅2.4GHz，而没有在PCMar...
基于6个网页-相关网页
此两种简单的管线及上纯量设计，均能透过允许单一处理器在一个时脉循环完成一个指令（Instruction per cycle, IPC）[ipcrate] ，提升指令管线化的效能。
基于2个网页-相关网页
The POWER6 chip has two hardware instruction threads that are both capable of issuing multiple instructions per cycle, which causes a boost in performance.
POWER 6处理器有两个能够在每个处理器周期发出多条指令的硬件指令线程，从而改善了性能。
The POWER5 chip has two hardware instruction threads that are both capable of issuing multiple instructions per cycle, which causes a boost in performance.
POWER 5芯片有两个硬件指令线程，在每个周期都能够执行多个指令，这可以提高性能。
By knowing instruction retired per cycle, the system knows how fast the current application is executing inside the processor.
通过知晓每循环的指令重试，系统就知晓了处理器内部正在执行的当前应用程序有多快。
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