Experiment result showed, the topology can make the device get to high Power Factor (PF), low Total Harmonic Distortion (THD) of input current, low ripple of output voltage, and high efficiency.
实验结果表明，应用该电路拓扑的实验装置，其功率因数较高，输入电流的总谐波畸变较低，输出电压纹波小，而且整个装置的效率也比较高。
The algorithm yields low common mode voltage and current, acceptable PWM ripple at the input and output of the inverter, and has no overvoltage problems unlike AZSPWM1.
该算法产量低共模 电压和电流，在可接受哒PWM输入纹波 和输出哒逆变器，并没有过电压 提问题不要像AZSPWM1。
Compared with traditional circuit, it has lower output voltage ripple, lower load adjustment rate and lower input voltage adjustment rate.
与传统方法相比，该方法具有电压纹波小、负载调整率和电压调整率低的特点。
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