two input adder 半加器
three input adder 三输入端加法器
two-input adder 半加法器 ; 二输入端加法器
three-input binary adder 三输入端二进加法器
adder left input register 加法器左输入缓存器
three-input amplitude adder 三输入端振幅加法器
three input amplitude adder 三输入端振幅加法器
Frequency controlled data (m) plus an accumulative phase data output by a phase register in an N-bit adder when a clock pulse comes, the result is sent to the input port of the phase register.
每来一个时钟脉冲，N位加法器将频率控制数据m与相位寄存器输出的累加相位数据相加，并将结果送相位寄存器输入端。
Finally the generator can automatically select the best partition point for different types of adders according to various of input delays in the final adder stage.
最后在末级加法器阶段，生成器能根据到达的时延不同自动选择不同加法器最优的分段。
Addend and the summand input, and digital and carry the output device is a half adder.
加法器是产生数的和的装置。加数和被加数为输入，和数与进位为输出的装置为半加器。
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