Through the synthesis of MAC circuit, it validates that the ideas and methods presented in the paper do well to reduce the critical path delay and circuit gates.
电路综合实验表明采用本文所提出思想和方法可以有效减少MAC关键路径时延和电路门数。
Firstly, false paths in static timing analysis and the algorithm to sensitize paths are presented, and then some factors affecting gates and interconnects delay are discussed.
首先,文章讨论了静态时序分析中的伪路径问题以及路径敏化算法,分析了影响逻辑门和互连线延时的因素。
The dynamic performance of the gates and the advantages of internal structure of tri-state gate control are also presented. Results of the averaged time delay design are given. which have bee...
同时介绍了该分频器各级门的动态特性以及内部用三态门控制结构的优点,给出了平均延迟时间的设计结果,该设计已应用于高频时钟芯片的大批量生产中。
应用推荐