The design method for the efficient time-varying network architecture of the fractional multiple sampling rate converter is presented and its field programmable gate array (FPGA) is implemented.

提出了分数倍抽样率转换器的高效时变网络结构的设计方法，并用现场可编程门阵列(FPGA)实现。

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An improved fuzzy neural network can be developed to implement synchronous control for the double hanging point gate.

利用一种改进的模糊神经网络实现双吊点闸门的同步控制。

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And then using Boolean equations containing gate variables and means of OBDD, an efficient algorithm for computing the K-terminal reliability of a network is also proposed.

然后，基于具有门限变量的布尔方程和有序二分决策图方法(OBDD)，给出计算k -终端网络可靠度算法。

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