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A novel encoding scheme with high speed and low power is proposed for folding and interpolating ADC.
提出了一种新的适用于折叠插值型adc的高速低功耗的编码器。
With the nice features in speed, resolution, power consumption and proportion, folding and interpolating analog-digital converter becomes a study hotspot in recent years.
折叠内插结构模数转换器由于在速度、分辨率、功耗和芯片面积等方面具有良好的特性而成为了近年来的一个研究热点。
Bandwidth and offset of CMOS folding preprocessing circuit are the main factors, which limit the dynamic and static characteristics of folding-interpolating ADC.
CMOS折叠预处理电路的带宽和失调是限制折叠内插式adc的动态和静态特性的主要原因之一。
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