据台积电内部规划，2007年封装的将主要着力于65纳米制程，包括无铅封装及晶片尺寸覆晶封装(Flip Chip CSP)，2008年则将跨入45纳米制程的封装。包括打线(wire bond)及无铅，晶片尺寸覆晶封装等。
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Chip scale package (CSP) for flip-chip on hard substrates and wafer re-distribution is studied, and its process flow is described.
对刚性基板倒装式和晶圆再分布式两种结构的芯片级封装（CSP）进行了研究，描述了CSP的工艺流程；
And the important role of advanced packagings such as CSP, BGA and Flip-chip technology in the microelectronics is described as well.
论述了如csp、BGA及倒装芯片等先进封装技术在微电子工业中所发挥的重要作用。
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