With the same number of multipliers in FPGA, the order of FIR filter in receiver with above optimum structure is nearly4 times than it implemented in direct way.
在FPGA乘法器资源相同的条件下，采用最优结构设计的接收机内部fir滤波器阶数比直接实现形式高了近4倍。
In this paper, the problem of optimal design of interpolation filter for all digital receiver is discussed.
本文讨论了全数字接收机中插值滤波器的优化设计问题。
The design of interpolation filter is one of the important problems for all digital implementation of receiver.
插值滤波器的设计问题是接收机全数字化实现的核心问题之一。
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