...com豆丁网 架构的 MRAM 读写机制， 主要使用三条控制线来完成，分别为位元线（Bit line， BL）、写入字元线（Write Word line，WWL）及读取 字元线（Read Word line，RWL）。
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pillar write word line 柱状写字线
During a write operation, the write word line is asserted.
在写入操作期间，该写入字线被断言。
An access transistor (54) is coupled between each storage node (SN, SNB) and a write bit line (WWB0) and controlled by a write word line (WWL0).
存取晶体管(54)耦合在每个存储节点(SN, snb)和写入位线(WWB0)之间，并且由写入字线(WWL0)控制。
At the end of the write operation, the write word line is de-asserted, allowing the cross-coupled inverters (40) to function normally and hold the logic state of the storage node (SN).
在写入操作结尾，写入字线被去断言，允许交叉耦合的反相器(40)正常工作并且保持存储节点(SN)的逻辑状态。
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