Network time-delay simulator with FPGA as the core was designed according to the needs of doing network measurement within laboratory area in this paper.
本文针对在实验室范围内进行网络测量的需要，设计了以FPGA为核心的网络延时模拟器。
Through lab simulator test and lake trial, the underwater signal processing module is proved to be satisfied with the system's demand and is with high time delay precision and reliability.
通过实验室的模拟器调试和湖试的验证，证明了水声信号处理模块符合系统要求，具备较高的时延估计精度及可靠性。
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