It is found that ESR decreases with decrease of the active dielectric layer thickness, and DC resistance decreases with the increases of active dielectric layer number.

研究表明，等效串联电阻随着有效介质层厚度的降低而降低，直流电阻随着有效介质层数的增加而降低。

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In addition, the poly tiles themselves increase the thickness of the isolation between active silicon regions when it must serve as a self-aligned blocking layer for an ion implantation step.

另外，当有源硅区之间的隔离必须充当一离子注入步骤的一自行对准阻挡层时，所述多晶硅瓦片本身增加所述隔离的厚度。

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Changes of shallow layer ground temperature can indicate the changes in active layer thickness.

浅层土壤温度的变化可以指示活动层厚度变化。

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