The fabrication process of a compact planar waveguide etched-grating(EDG) demultiplexer based on silicon-on-insulator(SOI) is studied.

研究了基于绝缘材料上的硅（SOI）材料的平面波导刻蚀光栅分波器的主要制作工艺。

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Based on building the mathematical model of scanning process of Length alterable Line scanning Laser rapid prototyping system, a zoning algorithm for planar polygon is put forward.

在建立激光变长线快速成型系统加工过程的数学模型的基础上，提出了一种可对任意平面图形进行分区处理的分区算法。

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The temperature control of the producing process of a planar carrier catalytic element has been operated manually so far, which has influence on both identity and productivity of the element.

平面型载体催化元件制作过程的温度控制一直沿用手工操作，从而使元件的一致性与成品率受到较大影响。

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While the FinFET process offers significant power and performance benefits compared to the traditional planar process, the move from two-dimensional transistors to three-dimensional transistors introduces several new IP and EDA tool challenges such as modeling.

ENGADGET: Samsung reveals its first 14nm FinFET test chip, should offer substantial power improvements in future silicon

The 20nm 64Gb NAND uses a planar cell structure -- the first in the industry -- to overcome the inherent difficulties that accompany advanced process technology, enabling performance and reliability on par with the previous 25nm generation.

ENGADGET: Intel ships SSD 335 as its first drive with 20nm flash, asks just a little to stay cutting-edge