The paper proposed a new Selected Variable-length Input Coding (SVIC) for System on Chip (SOC) test data compression.
本文针对SOC测试数据压缩，提出了一种新的可挑选变长输入编码(SVIC)方案。
A test data compression scheme based on fixed and variable length coding (FAVLC) is presented, by using which the test data can be compressed efficiently.
文章提出了一种混合定变长码的测试数据压缩方案，该方案可以有效压缩芯片测试数据量。
In order to reduce the volume of IC test data, an index coding compression scheme based on test data partition merging is proposed.
为降低集成电路的测试数据量，提出一种分组合并的索引编码压缩方案。
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