Static timing analysis is widely applied in timing verification because of its high speed and great capacity. The gate delay computing is a critical part of static timing analysis.

静态时序分析由于速度快和容量大而广泛应用于时序验证，而门延时的计算则是静态时序分析中的关键部分。

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In this paper, on the basis of static timing analysis, a new method is employed to enhance the efficiency of FPGA partition by extracting the information of critical path-delay.

文章在静态时序分析的基础上，提出了一种利用关键路径时延信息提高FPGA分割效率的方法。

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Firstly, false paths in static timing analysis and the algorithm to sensitize paths are presented, and then some factors affecting gates and interconnects delay are discussed.

首先，文章讨论了静态时序分析中的伪路径问题以及路径敏化算法，分析了影响逻辑门和互连线延时的因素。

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