The sequence control circuit of DATA collection is designed with finite state machine(FSM) of VHDL.
用VHDL（甚高速集成电路硬件描述语言）有限状态机设计了数据采集时序的控制电路。
This paper extends the sequence model approximation (SMA) approach to hierachical control of large-scale steady state systems.
本文将序列模型逼近法推广到稳态大系统的递阶优化与控制中去。
This pager deduces the state transition matrices of CDTLS, both in time domain and in sequence domain, and presents a method solving the optimal control problem of CDTLS by Walsh transformation.
本文分析了CDTLS在时间域及序率域上的传递特性，提出了一种求解该优化问题的沃尔什变换算法。
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