Based on the analysis of the complexity and hardware architecture of FFT, the proposed processor adopts radix-4 DIF algorithm, pipelined architecture and fixed-point operation.

在分析了FFT算法的复杂度和硬件实现结构的基础上，处理器采用了按频率抽取的基- 4算法，分级流水线以及定点运算结构。

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This design adopts the algorithm of radix-4 and decimation-in-time (DIT) to devise a real-time FFT hardware processor with practicality.

设计采用基4 算法设计了一个具有实用价值的FFT 实时硬件处理器。

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This paper studies the parallelism of the different stages of decimation in time radix 2 FFT algorithm, designs the butterfly and scramble kernels and implements 2d FFT on GPU.

本文研究了基2的时域抽取快速傅立叶变换各阶段的并行性，并据此设计了相应的蝶形和倒序运算核，在GPU上实现了二维fft运算。

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