Lead ASIC frond-end design team to complete Synthesis, STA, Equivelant Check, Post Layout Simulation, DFT, ATE, Power Control. Make sure RTL code is ok for chip implement.

负责带领整个团队实施芯片的综合、静态时序分析、逻辑一致性分析、后仿真、DFT、ATE、功耗控制。从芯片实现的角度对模块的RTL代码和芯片的RTL代码进行把关。

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Design flow of analog circuit begins with drawing schematic and includes simulation, layout, DRC/LVS check, parasitic extraction and post-simulation.

在完成版图设计后，还进行了几何规则 检查和版图与 电路一致性的 检查。

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