A path delay fault testing generation algorithm for digital circuits based on neural network is proposed because the testing generation for path delay fault in digital circuits is more difficult.
针对数字电路路径时滞故障测试生成较难的问题，提出了基于神经网络的数字电路路径时滞故障测试生成算法。
This paper presents an approach to delay testing with duplicating variable observation points, which provides a high path delay fault coverage by testing a small number of paths.
本文提供了一种使用双倍可变观测点进行时滞测试的方法，保证了只需要测试少量通路就能完成整个电路的时滞测试。
At first it introduces the transition fault module and the path delay fault module, including two specific methods which are used in testing. Then it summarizes several important vectors of testing.
首先介绍了转换故障模型和路径延迟故障模型，以及测试时采用的具体的两种测试方法，然后总结了一些测试时要注意的事项。
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