... 制造相关测试(Manufacturing Related Test) 嵌入式汇流排(On Chip Buses) 系统层次设计(System Level Design) ...
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on-chip buses 片上总线
The design of SOC usually adopts hierarchical on-chip-bus architecture, different IPs are integrated on different types of buses.
SOC设计通常采用层次化片上总线体系结构,不同的IP集成在不同类型的总线上。
In the SOC design, the hierarchical on-chip-bus architecture is usually adopted, and different IPs are integrated on different types of buses.
SOC设计通常采用层次化片上总线的体系结构,不同的IP集成在不同类型的总线上。
In the meantime, the module takes advantage of on-chip cache to reduce the pressure on the system buses.
同时,该设计还使用片上缓存方式,降低了系统总线的占用率。
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