The low power on-chip buses encoding technique is resultful for reducing the power consumption of DSP buses, so it is meaning for DSP low power design.

同时总线编码技术对于降低DSP总线功耗有明显的效果，所以这一技术对DSP低功耗设计有重要的意义。

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The design of SOC usually adopts hierarchical on-chip-bus architecture, different IPs are integrated on different types of buses.

SOC设计通常采用层次化片上总线体系结构，不同的IP集成在不同类型的总线上。

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In the SOC design, the hierarchical on-chip-bus architecture is usually adopted, and different IPs are integrated on different types of buses.

SOC设计通常采用层次化片上总线的体系结构，不同的IP集成在不同类型的总线上。

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The third-generation platform architecture consists of a multi-core SSD controller integrated with multiple high-speed serial on-chip buses and embedded processors, achieving high-speed data transfer between host and storage device.

ENGADGET: BiTMICRO's next-gen SSD controller to deliver blazing speed and big storage in 2012