This dissertation's focus is on the investigation of the design and implementation of real-time multi-target capture module and distance operation coprocessor, which are implemented with FPGA.
本文重点研究了基于FPGA的实时多目标捕获模块和距离运算协处理器的设计与实现。
The radix-2 decimation-in-time algorithm based on 16-bit fixed-point operation and pipeline architecture are adopted in the core module IFFT(Inverse Fast Fourier Transform).
核心模块快速傅立叶逆变换（IFFT）采用基于16位定点运算的基-2时间抽取算法和流水线结构。
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