Interconnect wire delay is a very important question that must to be resolved in deep submicron IC design.

深亚微米集成电路的互连线延迟是设计中需十分重视并必须解决的问题。

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The factors that affect the interconnect wire delay and the resolution ways from to lower the signal swing and change switch threshold value aspect are described in this paper.

本文讨论了影响互连线延迟的因素，并讨论了从降低信号摆幅、改变开关阈值方面解决延迟、功耗等问题。

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