This paper presented an innovative analytical delay model for RLC interconnects utilized in the estimation of interconnect delay for deep submicrometer VLSI circuits.
提出了用来评估深亚微米vlsi电路中rlc互连延时的一种新的解析延时模型。
Based on the theory of the probability interpretation algorithm, a statistical model of RLC interconnect delay in the presence of process variations was put forward.
基于概率解释算法的原理，提出了一种考虑工艺波动的RLC互连延时统计模型，该模型使用了对数正态分布函数。
In this thesis, the interconnect model in the SOC design, and the delay, power and design method for layout design are investigated from the perspective of interconnect design.
本文主要针对SOC中的连线模型以及从连线设计角度对版图设计中的时延、功耗以及设计方法进行研究。
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