The POWER6 chip has two hardware instruction threads that are both capable of issuing multiple instructions per cycle, which causes a boost in performance.

POWER 6处理器有两个能够在每个处理器周期发出多条指令的硬件指令线程，从而改善了性能。

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The POWER5 chip has two hardware instruction threads that are both capable of issuing multiple instructions per cycle, which causes a boost in performance.

POWER 5芯片有两个硬件指令线程，在每个周期都能够执行多个指令，这可以提高性能。

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The POWER5 microprocessor doubles that throughput by collecting two groups of up to five instructions per clock cycle and completing two groups per clock cycle.

POWER 5微处理器使此吞吐量增加了一倍，每个时钟周期收集两组指令(每组最多有五个)，并在每个时钟周期内完成两组指令。

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Things like the number of computer instructions per clock cycle, the bandwidth of the RAM bus, and the overall efficiency of the architecture are at least as important as the raw clock speed at which a processor runs.

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What really matters is how much work a chip can accomplish, a figure measured by the number of instructions executed per clock cycle.

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