...恢复；过采样；输入延时单元；现场可编程逻辑阵列 [gap=494]Key words: clock and data recovery;oversampling;input delay unit;field programmable logic arrays ...
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It comprises of four basic unit: input delay, filter, register bank, and control unit.
这种结构由四部分构成：输入延迟单元、寄存器单元、滤波器单元和控制单元。
A semiconductor memory is used as a delay unit. Short-term averager and long-term averager integrate the input signals.
采用半导体存储器延迟信号，短时间平均器与长时间平均器对输入信号积分。
The input ends of positive phase and negative phase of the first time-delay unit are respectively connected with the output ends of positive phase and negative phase of the last time-delay unit.
每一级正相和负 相信号输出端分别与各输出缓冲电路的正相和负相输入端相连。
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