CLK-IN Clock Input 时钟信号输入
My question is, how do I know what the input CLK frequency should be?
我的问题是，我怎么知道输入时钟频率应该是多少？
I've read the datasheet but can't find any reference to specifying an input CLK frequency.
我读过的数据表，但找不到任何参考指定一个输入时钟频率。
Data is read serially by the Driver IC on the input CLK rising edge once the STB input line goes low.
数据读取连续的驱动ic的输入时钟的上升沿一旦机顶盒输入线变低。
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